• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A frequency dividing circuit and its control method is described. In this circuit, the frequency dividing input circuit is connected with a first counting circuit and a counting and setting circuit. The first counting circuit is connected with a second counting circuit, a first comparing circuit, a first threshold input circuit and the counting and setting circuit. The second counting circuit is connected with the counting and setting circuit, a second threshold input circuit and a second comparing circuit. The first comparing circuit is connected with the first threshold input circuit and the second comparing circuit. The second threshold input circuit is connected with the second comparing circuit. The second comparing circuit is connected with the counting and setting circuit. This method achieves frequency division by setting two thresholds and combining the output and input characteristics of comparator and counter by changing the dial switch without any circuit modification.
    公开号:NL2016141A
    申请号:NL2016141
    申请日:2016-01-22
    公开日:2017-01-20
    发明作者:Kang Cheng
    申请人:Univ Fu Zhou；
    IPC主号:
    专利说明:

    A new low cost frequency dividing circuit and its control method
    Technical Field
    The invention relates to a new low cost frequency dividing circuit and its control method.
    Technical Background of the invention
    The traditional frequency dividing circuit is shown in Figure 1, which is realized by series T trigger, the disadvantages are: If we want to change the frequency speed in use, we not only have to change the hardware connection of the circuit, but also need to increase the number of necessary components, which increase the unnecessary costs and which is more cumbersome. In addition, the frequency of the frequency dividing circuit is only 2 times, such as 2,8,16, and it can not divide the frequency in arbitrary multiples, which greatly affecte the convenience of the circuit. Due to the widespread application of the frequency dividing circuit, it is urgent to put forward a kind of frequency dividing circuit which is not limited to the basic multiples of 2, and which is simple and efficient and spands low cost.
    Summary of the utility model
    The invention aims to provide a new low cost frequency dividing circuit and its control method in order to overcome the defects existing in the prior art and achieve the setting of arbitrary frequency dividing ratio.
    To achieve the above purpose, the technology options of this invention are: a new low cost frequency dividing circuit, including a frequency dividing input module, the first end of the frequency dividing input module is connected to the first end of a first counting module, the second end of the first counting module is connected to the first end of a first threshold input module, the third end of the first counting module is connected to the fisrt end of a first comparing module, the fourth end of the first counting module is connected to the first end of a second counting module, the second end of the first threshold input module is connected to the second end of the first comparing module, the second end of the second counting module is connected to the first end of a second threshold input module, the third end of the second counting module is connected to the first end of a second comparing module, the second end of the second threshold input module is connected to the second end of the second comparing module, the third end of the second comparing module is connected to the third end of the first comparing module, the fourth end of the second comparing module is used as the output end of the new low cost frequency dividing circuit and is connected to the first end of a counting and setting module, the second end of the counting and setting module is connected to the second end of the frequency dividing input module, the third end of the counting and setting module is connected to the fifth end of the first counting module and the fourth end of the second counting module.
    Further, the frequency dividing input module includes a first NAND circuit and a second NAND circuit, the first input end of the first NAND circuit is used to input reduced pulse signal, the first input end of the second NAND circuit is used to input plus pulse signal, the second input end of the first NAND circuit is connected to the second input end of the second NAND circuit, which is used as the second end of the frequency dividing input module, the output end of the first NAND circuit and the output end of the second NAND circuit is both connected to the first counting module.
    Further, the first counting module includes a first counter 40193, the CP+ end of the first counter 40193 is connected with the output end of the second NAND circuit, the CP- end of the first counter 40193 is connected with the output end of the first NAND circuit, the R end of the first counter 40193 is used as the fifth end of the first counting module.
    Further, the first comparing module includes a first comparator 4585; the AO end , A1 end, A2 end and A3 end of the first comparator 4585 are respectively connected to the Q1 end, Q2 end, Q3 end, Q4 end of the first counter 40193; the (A>B)IN end and the (A=B)IN end of the first comparator 4585 is connected with high level, the (A<B)IN end of the first comparator 4585 is earthed.
    Further, the first threshold input module includes a first dial switch SI, the first input end to the fourth input end of the first dial switch SI are both connected with high level, the first output end to the fourth output end of the first dial switch SI are respectively connected to the DPI end, DP2 end, DP3 end, DP4 end of the first counter 40193, the first output end of the first dial switch SI is also connected with the first end of a fourth resistance(R4) and the B3 end of the first comparator 4585, the second output end of the first dial switch S1 is also connected with the first end of a third resistance(R3) and the B2 end of the first comparator 4585, the third output end of the first dial switch SI is also connected with the first end of a second resistance(R2) and the B1 end of the first comparator 4585, the fourth output end of the first dial switch SI is also connected with the first end of a first resistance(Rl) and the BO end of the first comparator 4585; the second end of the first resistance(Rl), the second end of the second resistance(R2), the second end of the third resistance(R3) and the second end of the fourth resistance(R4) are both earthed.
    Further, the second counting module includes a second counter 40193, the CP+ end of the second counter 40193 is connected to the CO end of the first counter 40193, the CP- end of the second counter 40193 is connected to the BO end of the first counter 40193, the R end of the second counter 40193 is used as the fourth end of the second counting module, the CO end of the second counter 40193 is connected to the PE end of the first counter 40193 and the PE end of the second counter 40193 .
    Further, the second comparing module includes a second comparator 4585; the A0 end , A1 end, A2 end and A3 end of the second comparator 4585 are respectively connected to the Q1 end, Q2 end, Q3 end, Q4 end of the second counter 40193; the (A>B)IN end of the second comparator 4585 is connected with high level, the (A=B)IN end of the second comparator 4585 is connected to the (A=B)OUT end of the first comparator 4585, the (A<B)IN end of the second comparator 4585 is connected to (A<B)OUT end of the first comparator 4585, the (A>B)OUT end of the second comparator 4585 is used as fourth end of the second comparing module.
    Further, the second threshold input module includes a second dial switch S2, the first input end to the fourth input end of the second dial switch S2 are both connected with high level, the first output end to the fourth output end of the second dial switch S2 are respectively connected to the DPI end, DP2 end, DP3 end, DP4 end of the second counter 40193, the first output end of the second dial switch S2 is also connected with the first end of a eighth resistance(R8) and the B3 end of the second comparator 4585, the second output end of the second dial switch S2 is also connected with the first end of a seventh resistance(R7) and the B2 end of the second comparator 4585, the third output end of the second dial switch S2 is also connected with the first end of a sixth resistance(Ró) and the B1 end of the second comparator 4585, the fourth output end of the second dial switch S2 is also connected with the first end of a fifth resistance(R5) and the BO end of the second comparator 4585; the second end of the fifth resistance(R5), the second end of the sixth resistance(Ró), the second end of the seventh resistance(R7) and the second end of the eighth resistance(R8) are both earthed.
    Further, the counting and setting module includes a third NAND circuit and a NOR circuit, the first input end of the third NAND circuit is used as the second end of the counting and setting module, the second input end of the third NAND circuit is used as the first end of the counting and setting modul, the output end of the third NAND circuit is connected to the input end of the NOR circuit, the output end of the NOR circuit is used as the third end of the counting and setting module.
    Further, a control method of a new low cost frequency dividing circuit according to the content mentioned above is : set the first threshold N by the first dial switch S1 in the first threshold input module, set the second threshold M by the second dial switch S2 in the second threshold input module, when the setting is completed, provide power to all the modules of the frequency dividing circuit, the frequency dividing input module input the signal to be divided to the CP+ end of the first counter 40193 in first counting module, the first counter 40193 counts the signal to be divided, the first comparator 4585 in first comparing module recieves the first counting output from the output end of the first counter 40193, then compare the first counting output with the the first threshold N, the CO end of the first counter 40193 gives a pulse when the first counting output is equal to the first threshold N; the first counter 40193 transmits the pulse to the CP+ end of the second counter 40193, the second counter 40193 counts the pulse; the second comparator 4585 in second comparing module recieves the second counting output from the output end of the second counter 40193, then compare the second counting output with the the second threshold M, the (A>B) OUT end of the second comparator 4585 gives frequency pulse signal when the second counting output is equal to the second threshold M, in order to achieve the M*16+N frequency division of the signal to be divided; transmit the frequency pulse signal to the R end of the first counter 40193 and the R end of the second counter 40193 by the counting and setting module for resetting and restart counting, where N or M is a positive integer greater than or equal to 1.
    Compared with the prior art, the invention has the following advantages: The invention relates to a new low cost frequency dividing circuit and its control method, which can divide the frequency in any integer multiple, and which is not limited to the existing frequency dividing circuit that can only divide the frequency in 2 times. The invention can achieve frequency division by setting two thresholds and combining the output and input characteristics of comparator and counter. The invention can set frequency division multiple with any integer simply and efficiently only by changing the dial switch without any hardware circuit modification. The invention greatly reduce the cost not using any programmable logic devices or micro control processor.
    Brief description of the drawings
    Figure 1 shows the circuit diagram of the frequency division circuit used in the conventional technology.
    Figure 2 shows the circuit principle diagrama of the new low cost frequency dividing circuit in this invention.
    Figure 3 shows the schematic diagram of circuit connection of the new low cost frequency dividing circuit in this invention.
    Detailed Description of the invention
    To allow the above features and advantages of this invention become more fully understood, especially cite the example below, and with the accompanying drawings, described in detail below, but the invention is not limited to this.
    Example 1: As shown in figure 2, a new low cost frequency dividing circuit, including a frequency dividing input module, the first end of the frequency dividing input module is connected to the first end of a first counting module, the second end of the first counting module is connected to the first end of a first threshold input module, the third end of the first counting module is connected to the fisrt end of a first comparing module, the fourth end of the first counting module is connected to the first end of a second counting module, the second end of the first threshold input module is connected to the second end of the first comparing module, the second end of the second counting module is connected to the first end of a second threshold input module, the third end of the second counting module is connected to the first end of a second comparing module, the second end of the second threshold input module is connected to the second end of the second comparing module, the third end of the second comparing module is connected to the third end of the first comparing module, the fourth end of the second comparing module is used as the output end of the new low cost frequency dividing circuit and is connected to the first end of a counting and setting module, the second end of the counting and setting module is connected to the second end of the frequency dividing input module, the third end of the counting and setting module is connected to the fifth end of the first counting module and the fourth end of the second counting module.
    In this example, the frequency dividing input module includes a first NAND circuit U1 and a second NAND circuit U2 , the first input end of the first NAND circuit U1 is used to input reduced pulse signal, the first input end of the second NAND circuit U2 is used to input plus pulse signal, the second input end of the first NAND circuit U1 is connected to the second input end of the second NAND circuit U2, which is used as the second end of the frequency dividing input module, the output end of the first NAND circuit UI and the output end of the second NAND circuit U2 is both connected to the first counting module.
    In this example, as shown in figure 3 ,the first counting module includes a first counter 40193, the CP+ end(pin 5) of the first counter 40193 is connected with the output end of the second NAND circuit U2, the CP- end(pin 4) of the first counter 40193 is connected with the output end of the first NAND circuit Ul, the R end(pin 14) of the first counter 40193 is used as the fifth end of the first counting module, which is connected to the output end of the NOR circuit in counting and setting module.
    In this example, the first comparing module includes a first comparator 4585; the AO end(pin 10), A1 end(pin 7), A2 end(pin 2) and A3 end(pin 15) of the first comparator 4585 are respectively connected to the Q1 end(pin 3), Q2 end(pin 2), Q3 end(pin 6), Q4(pin 7) end of the first counter 40193; the (A>B)IN end(pin 4) and the (A=B)IN end(pin 6) of the first comparator 4585 is connected with high level, the (A<B)IN end(pin 5) of the first comparator 4585 is earthed.
    In this example, the first threshold input module includes a first dial switch Sl( which is a 4 digit dialing switch), the first input end to the fourth input end of the first dial switch S1 are both connected with high level, the first output end to the fourth output end of the first dial switch SI are respectively connected to the DPI end(pin 15), DP2 end(pin 1), DP3 end(pin 10), DP4 end(pin 9) of the first counter 40193, the first output end of the first dial switch SI is also connected with the first end of a fourth resistance(R4) and the B3 end(pin 14) of the first comparator 4585, the second output end of the first dial switch SI is also connected with the first end of a third resistance(R3) and the B2 end(pin 1) of the first comparator 4585, the third output end of the first dial switch SI is also connected with the first end of a second resistance(R2) and the B1 end(pin 9) of the first comparator 4585, the fourth output end of the first dial switch SI is also connected with the first end of a first resistance(Rl) and the B0 end(pin 11) of the first comparator 4585; the second end of the first resistance(Rl), the second end of the second resistance(R2), the second end of the third resistance(R3) and the second end of the fourth resistance(R4) are both earthed.
    In this example, as shown in figure 3,the second counting module includes a second counter 40193, the CP+ end(pin 12) of the second counter 40193 is connected to the CO end(pin 12) of the first counter 40193, the CP- end(pin 4) of the second counter 40193 is connected to the BO end(pin 13) of the first counter 40193, the R end(pin 14) of the second counter 40193 is used as the fourth end of the second counting module, the CO end(pin 12) of the second counter 40193 is connected to the PE end(pin 11) of the first counter 40193 and the PE end(pin 11) of the second counter 40193 .
    In this example, the second comparing module includes a second comparator 4585; the A0 end(pin 10) , A1 end(pin 7), A2 end(pin 2) and A3 end(pin 1) of the second comparator 4585 are respectively connected to the Q1 end(pin 3), Q2 end(pin 2), Q3 end(pin 6), Q4 end(pin 7) of the second counter 40193; the (A>B)IN end(pin 4) of the second comparator 4585 is connected with high level(5V), the (A=B)IN end(pin 6) of the second comparator 4585 is connected to the (A=B)OUT end(pin 3) of the first comparator 4585, the (A<B)IN end(pin 6) of the second comparator 4585 is connected to (A<B)OUT end(pin 12) of the first comparator 4585, the (A>B)OUT end(pin 13) of the second comparator 4585 is used as fourth end of the second comparing module.
    In this example, as shown in figure 3,the second threshold input module includes a second dial switch S2(which is a 4 digit dialing switch), the first input end to the fourth input end of the second dial switch S2 are both connected with high level, the first output end to the fourth output end of the second dial switch S2 are respectively connected to the DPI end(pin 15), DP2 end(pin 1), DP3 end(pin 10), DP4 end(pin 9) of the second counter 40193, the first output end of the second dial switch S2 is also connected with the first end of a eighth resistance(R8) and the B3 end(pin 14) of the second comparator 4585, the second output end of the second dial switch S2 is also connected with the first end of a seventh resistance(R7) and the B2 end(pin 1) of the second comparator 4585, the third output end of the second dial switch S2 is also connected with the first end of a sixth resistance(Ró) and the B1 end(pin 9) of the second comparator 4585, the fourth output end of the second dial switch S2 is also connected with the first end of a fifth resistance(R5) and the B0 end(pin 11) of the second comparator 4585; the second end of the fifth resistance(R5), the second end of the sixth resistance(R6), the second end of the seventh resistance(R7) and the second end of the eighth resistance(R8) are both earthed.
    In this example, as shown in figure 3,the counting and setting module includes a third NAND circuit U4 and a NOR circuit U3, the first input end of the third NAND circuit U4 is used as the second end of the counting and setting module(which is connected to the second input end of the first NAND circuit U1 and the second input end of the second NAND circuit U2), the second input end of the third NAND circuit is used as the first end of the counting and setting modul(which is connected to the (A>B)OUT end of the second comparator 4585), the output end of the third NAND circuit U4 is connected to the input end of the NOR circuit U3, the output end of the NOR circuit U4 is used as the third end of the counting and setting module(which is connected to the R end of the first counter 40193 and the R end of the second counter 40193).
    In order to let the technical personnel in the field to fully understand the invention of a new low cost frequency dividing circuit, following are the control method combined with the specific instructions. A control method of a new low cost frequency dividing circuit according to the content mentioned above is : set the first threshold N by the first dial switch SI in the first threshold input module, set the second threshold M by the second dial switch S2 in the second threshold input module, when the setting is completed, provide power to all the modules of the frequency dividing circuit, the frequency dividing input module input the signal to be divided to the CP+ end of the first counter 40193 in first counting module, the first counter 40193 counts the signal to be divided, the first comparator 4585 in first comparing module recieves the first counting output from the output end of the first counter 40193(the Q1 end to Q4 end of the first counter 40193), then compare the first counting output with the the first threshold N, the CO end of the first counter 40193 gives a pulse when the first counting output is equal to the first threshold N; the first counter 40193 transmits the pulse to the CP+ end of the second counter 40193, the second counter 40193 counts the pulse; the second comparator 4585 in second comparing module recieves the second counting output from the output end of the second counter 40193(the Q1 end to Q4 end of the second counter 40193), then compare the second counting output with the the second threshold M, the (A>B) OUT end of the second comparator 4585 gives frequency pulse signal when the second counting output is equal to the second threshold M, in order to achieve the M*16+N frequency division of the signal to be divided; transmit the frequency pulse signal to the R end of the first counter 40193 and the R end of the second counter 40193 by the counting and setting module for resetting and restart counting, where N or M is a positive integer greater than or equal to 1.
    In this example, the first comparator 4585 and the second comparator 4585 are both 4 bit binary comparator. Input P to pin 10, pin 7, pin 2, pin 2 and pin 15, input Q to pin 11, pin 9, pin 1, pin 14, compare P with Q, if P>Q, pin 13 output high level; if P=Q, pin 3 output high level; if P<Q, pin 12 output high level.
    In this example, the first counter 40193 and the second counter 40193 are both 4 bit binary reversible counter. The counter plus 1 when pin 5 is at the rising edge, the counter minus 1 when pin 4 is at the rising edge. The counter can not work while the pin 4 and the pin 5 are both at the rising edge at the same time. The first counter 40193 and the second counter 40193 can both output counting value through pin 3, pin 2, pin 6 and pin 7.
    The invention described above is only a preferred embodiment, where the invention patent under this range equalization changes and modifications made, also belong to the scope of the invention.
    In short the invention can be described as follows:
    权利要求:
    Claims (10)
    [1]
    An inexpensive frequency division circuit, characterized in that it comprises a frequency division input module, a first output of the frequency division input module being coupled to a first input of a first counting module, a second input of the first counting module being coupled to a first output of a first threshold value input module , a third output of the first counting module is coupled to a first input of a first comparison module, a fourth output of the first counting module is coupled to a first input of a second counting module, a second output of the first threshold value input module is coupled to a second input of the first comparison module, a second input of the second counting module is coupled to a first output of a second threshold value input module, a third input of the second counting module is coupled to a first output of a second comparison module, a second input of the second threshold value input module is coupled i s with a second output of the second comparison module, a third input of the second comparison module is coupled to a third output of the first comparison module, wherein a fourth output of the second comparison module is used as the output of the low-cost frequency division circuit and is coupled to a first input of a counting and setting module, wherein a second output of the counting and setting module is coupled to a second input of the frequency division input module, a third output of the counting and setting module is coupled to a fifth input of the first counting module and a fourth input of the second counting module.
    [2]
    An inexpensive frequency division circuit according to claim 1, characterized in that the frequency division input module comprises a first and a second NAND circuit, wherein a first input of the first NAND circuit is used to input a decrease pulse signal, a first input of the second NAND circuit is used to input a plus pulse signal, a second input of the first NAND circuit being coupled to a second input of the second NAND circuit, which is used as the second input of the frequency division input module, the output of the first NAND circuit and the output of the second NAND circuit are both coupled to the first counting module.
    [3]
    An inexpensive frequency division circuit according to claim 2, characterized in that the first counting module comprises a first counter 40193, the CP + end of the first counter 40193 being coupled to the output of the second NAND circuit, the CP end of the first counter 40193 is coupled to the output of the first NAND circuit, the R end of the first counter 401934 being used as the fifth input of the first counting module.
    [4]
    An inexpensive frequency division circuit according to claim 3, characterized in that the first comparison module comprises a first comparator 4585, wherein the A0 end, the A1 end, the A2 end and the A3 end of the first comparator 4585 are coupled to the Q1, respectively Q2, Q3 and Q4 end of the first counter 40193, and wherein the (A> B) IN end and the (A = B) IN end of the first comparator 4585 is coupled to a high level and the (A <B) in 4585 is grounded at the end of the first comparator 4585.
    [5]
    An inexpensive frequency division circuit according to claim 4, characterized in that the first threshold value input module comprises a first dial switch S1, the first to fourth inputs of the first dial switch S1 being coupled to a high level, the first to with fourth output of the first dial switch S1 being coupled to the DPI, DP2, DP3 and DP4 end of the first counter 40193, respectively, the first output of the first dial switch S1 also being coupled to a first end of a fourth resistor ( R4) and the B3 end of the first comparator 4585, the second output of the first dial switch S1 is also coupled to a first end of a third resistor (R3) and the B2 end of the first comparator 4585, the third output of the first dial switch S1 is also coupled to a first end of a second resistor (R2) and the BI end of the first comparator 4585, the fourth output of the first dial switch S1 is also coupled is with a first end of a first resistor (R1) and the B0 end of the first comparator 4585, the second end of the first resistor (R1), the second end of the second resistor (R2), the second end of the third resistor (R3) and the second end of the fourth resistor (R4) are all grounded.
    [6]
    An inexpensive frequency division circuit according to claim 5, characterized in that the second counting module comprises a second counter 40193, wherein the CP + end of the second counter 40193 is coupled to the CO end of the first counter 40193, the CP end of the second counter is coupled to the BO end of the first counter 40193, the R end of the second counter is used as the fourth input of the second counter module, the CO end of the second counter 40193 is coupled to the PE end of the first counter 40193 and the PE end of the second counter 40193.
    [7]
    An inexpensive frequency division circuit according to claim 6, characterized in that the second comparison module comprises a second comparator 4585, wherein the A0 end, the A1 end, the A2 end and the A3 end of the second comparator 4585 are coupled to the Q1, respectively Q2, Q3 and Q4 end of the second counter 40193, and where the (A> B) IN end of the second comparator 4585 is coupled to a high level, the (A = B) IN end of the second comparator 4585 is coupled to the (A = B) OUT end of the first comparator 4585, the (A <B) IN end of the second comparator 4585 is coupled to the (A <B) OUT end of the first comparator 4585, the (A> B) The OUT end of the second comparator 4585 is used as the fourth output of the second comparison module.
    [8]
    An inexpensive frequency division circuit according to claim 7, characterized in that the second threshold value input module comprises a second dial switch S2, the first to fourth inputs of the second dial switch S2 being coupled to a high level, the first to and with the fourth output of the second dial switch S2 coupled to the DP1, DP2, DP3 and DP4 end of the second counter 40193, respectively, the first output of the second dial switch S2 also being coupled to a first end of an eighth resistor ( R8) and the B3 end of the second comparator 4585, the second output of the second dial switch S2 is also coupled to a first end of a seventh resistor (R7) and the B2 end of the second comparator 4585, the third output of the second dial switch S2 is also coupled to a first end of a sixth resistor (R6) and the B1 end of the second comparator 4585, the fourth output of the second dial switch S2 is also coupled is with a first end of a fifth resistor (R5) and the B0 end of the second comparator 4585, the second end of the fifth resistor (R5), the second end of the sixth resistor (R6), the second end of the seventh resistor (R7) and the second end of the eighth resistor (R8) are all grounded.
    [9]
    An inexpensive frequency division circuit according to claim 8, characterized in that the counting and setting module comprises a third NAND circuit and a NOR circuit, wherein a first input of the third NAND circuit is used as the second output of the counting and setting module wherein a second input of the third NAND circuit is used as the first input of the count-in setting module, the output of the NOR circuit being used as a third output of the counting and setting module.
    [10]
    A method for operating an geo-low frequency division circuit according to claim 9, characterized in that a first threshold value N is set in the first threshold value input module by the first dial circuit S1, a second threshold value M is set in the second threshold value input module by the first dial circuit S2, and - when the threshold values are set, all modules of the frequency division circuit are energized, the frequency division input module applies the signal to be shared to the CP + end of the first counter 40193 in the first counting module, - the first counter 40193 counts the signal to be shared the first comparator 4585 in the first comparison module receives the first count output from the output of the first counter 40193, then compares the first count output with the first threshold value N, the CO end of the first counter 40193 giving a pulse when the first count output is equal to the first threshold value N, the e first counter 40193 transmits the pulse to the CP + end of the second counter 40193 and the second counter 40193 counts the pulse, - the second comparator 4585 and the second comparison module receives a second count output from the output of the second counter 40193 and - then compares the second count output with the second threshold value M, the (A> B) OUT end of the second comparator giving a frequency pulse signal when the second count output is equal to the second threshold value M, in order to divide M * 16 + N of the signal to be shared, passing the frequency pulse signal to the R end of the first counter 40193 and the R end of the second counter 40193 by the counting and setting module for resetting and restarting the counting, where N and M an integer positive number greater than or equal to 1.
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    同族专利:
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    CN104901684B|2017-10-20|
    NL2016141B1|2017-05-29|
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    DE2451271A1|1974-10-29|1976-05-06|Licentia Gmbh|Pulse value convertor for electricity meters - pulses corresponding to mains voltage and load current converted through matching elements|
    GB2235556A|1989-06-29|1991-03-06|Birt Electronic Systems Ltd|Binary counting circuit|
    EP0480681A1|1990-10-09|1992-04-15|Mitsubishi Denki Kabushiki Kaisha|Semiconductor integrated circuit|
    EP1005164B1|1996-01-09|2002-11-20|SANYO ELECTRIC Co., Ltd.|Variable frequency divider|
    CN102102997A|2010-12-28|2011-06-22|威海华东电源有限公司|Random frequency division device for orthogonal serial output rotary encoder and implementation method thereof|
    CN204559543U|2015-04-25|2015-08-12|福州大学|A kind of novel low-cost frequency dividing circuit|CN107861597A|2017-11-30|2018-03-30|无锡中微爱芯电子有限公司|A kind of Anti-interference Design method being applied in MCU reset systems|
    法律状态:
    2020-09-02| MM| Lapsed because of non-payment of the annual fee|Effective date: 20200201 |
    优先权:
    申请号 | 申请日 | 专利标题
    CN201510199882.3A|CN104901684B|2015-04-25|2015-04-25|A kind of frequency dividing circuit and its control method|
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